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| www..com APA2120/2121 Stereo 2-W Audio Power Amplifier (with DC_Volume Control) Features * * * * * * * * * * Low operating current with 14mA Improved depop circuitry to eliminate turn-on and turn off transients in outputs High PSRR 32 steps volume adjustable by DC voltage with hysteresis 2W per channel output power into 4 load at 5V, BTL mode Two output modes allowable with BTL and SE modes selected by SE/BTL pin Low current consumption in shutdown mode (50A) Short Circuit Protection Power off depop circuit integration TSSOP-24 with or without thermal pad package General Description APA2120/1 is a monolithic integrated circuit, which provides precise DC volume control, and a stereo bridged audio power amplifiers capable of producing 2.7W(2.0W) into 3 with less than 10% (1.0%) THD+N. The attenuator range of the volume control in APA2120/1 is from 20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V) with 32 steps. The advantage of internal gain setting can be less components and PCB area. Both of the depop circuitry and the thermal shutdown protection circuitry are integrated in APA2120/1, that reduce pops and clicks noise during power up or shutdown mode operation. It also improves the power off pop noise and protects the chip from being destroyed by over temperature and short current failure. To simplify the audio system Applications * * NoteBook PC LCD Monitor or TV design, APA2120/1 combines a stereo bridge-tied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. Besides, the multiple input selection is used for portable audio system. Ordering and Marking Information A P A 2 1 2 0 /1 H a n d lin g C o d e Tem p. R ange P ackage C ode P ackage C ode R : T S S O P -P * Tem p. R ange I : - 4 0 to 8 5 C H a n d lin g C o d e TU : Tube T Y : T ra y TR : Tape & R eel A P A 2 1 2 0 /1 R : A P A 2 1 2 0 /1 XXXXX X X X X X - D a te C o d e * TSSOP-P is a standard TSSOP package with a thermal pad exposure on the bottom of the package. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 1 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Block Diagram LOUT+ MUX LLINEIN LHPIN RLINEIN RHPIN MUX V o lu m e C o n tro l LOUTLBYPASS BYPASS ROUT+ VOLUM E BYPASS HP/LINE H P /L IN E SE/BTL S E /B T L ROUTRBYPASS SHUTDOW N S h u td o w n ckt PCBEEP P C -B E E P ckt CLK C lo c k G e n For APA2121 Absolute Maximum Ratings (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter VDD VIN TA TJ TSTG TS VESD PD Supply Voltage Range Input Voltage Range, SE/BTL, HP/LINE, SHUTDOWN, PCBEN Operating Ambient Temperature Range Maximum Junction Temperature Storage Temperature Range Soldering Temperature,10 seconds Electrostatic Discharge Power Dissipation Rating -0.3 to 6 -0.3 to VDD+0.3 -40 to 85 Intermal Limited*1 -65 to +150 260 -3000 to 3000*2 -200 to 200*3 Intermal Limited Unit V V C C C C V Note: 1.APA2120/1 integrated internal thermal shutdown protection when junction temperature ramp up to 150C 2.Human body model: C=100pF, R=1500, 3 positives pulse plus 3 negative pulses 3.Machine model: C=200pF, L=0.5F, 3 positive pulses plus 3 negative pulses Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 2 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Recommended Operating Conditions Min. Supply Voltage, VDD High level threshold voltage, VIH Low level threshold voltage, VIL Common mode input voltage, VICM SHUTDOWN, PCBEN SE/BTL , HP/LINE SHUTDOWN, PCBEN SE/BTL , HP/LINE VDD-1.0 4.5 2 4 1.0 3 Max. 5.5 Unit V V V V Thermal Characteristics Symbol R THJA Parameter Thermal Resistance from Junction to Ambient in Free Air TSSOP-P* 45 K/W Value Unit * 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P package with solder on the printed circuit board. Electrical Characteristics VDD=5V, -20C Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 3 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Electrical Characteristics (Cont.) Operating Characteristics, BTL mode VDD=5V,TA=25C,RL=4, Gain=2V/V (unless otherwise noted) Symbol Parameter Test Condition THD=10%, RL=3, Fin=1kHz THD=10%, RL=4, Fin=1kHz PO THD=10%, RL=8, Fin=1kHz Maximum Output Power THD=1%, RL=3, Fin=1kHz THD=1%, RL=4, Fin=1kHz THD=0.5%, RL=8, Fin=1kHz THD+N Total Harmonic Distortion Plus Noise PSRR Power Ripple Rejection Ratio Xtalk S/N Channel Separation Signal to Noise Ratio PO=1.5W, RL=4, Fin=1kHz PO=1W, RL=8, Fin=1kHz VIN=0.1Vrms, RL=8, CB=1F, Fin=120Hz CB=1F, RL=8, Fin=1kHz PO=1.1W, RL=8, A_wieght 60 90 95 dB dB dB 1 APA2120/1 Min. Typ. Max. 2.7 2.3 1.5 2.0 1.9 1.1 0.05 0.07 % W Unit Operating Characteristics, SE mode VDD=5V,TA=25C,RL=4, Gain=1V/V (unless otherwise noted) Symbol Parameter Test Condition THD=10%, RL=8, Fin=1kHz PO THD=10%, RL=32, Fin=1kHz Maximum Output Power THD=1%, RL=8, Fin=1kHz THD=1%, RL=32, Fin=1kHz THD+N Total Harmonic Distortion Plus Noise PSRR Xtalk S/N Power Ripple Rejection Ratio Channel Separation Signal to Noise Ratio PO=250mW, RL=8, Fin=1kHz PO=75mW, RL=32, Fin=1kHz VIN=0.1Vrms, RL=8, CB=1F, Fin=120Hz CB=1F, RL=32, Fin=1kHz PO=75mW, SE, RL=32, A_wieght 48 100 100 dB dB dB APA2120/1 Min. Typ. Max. 400 110 320 90 0.08 0.08 % mW Unit Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 4 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Pin Description GND PCBEN VO LU M E LO U T+ LLIN EIN LH PIN PVDD RBYPASS LO U TLBYPASS BYPASS GND 1 2 3 4 5 6 7 8 9 10 11 12 APA2120 TO P View 24 23 22 21 20 19 18 17 16 15 14 13 GND R LIN EIN SHUTDO W N R O UT+ RHPIN VDD PVDD C LK R O UTSE/BTL PC-BEEP GND G ND H P/LIN E VO LUM E LO U T+ LLIN EIN LH PIN PVDD RBYPASS LO U TLBYPASS BYPASS G ND 1 2 3 4 5 6 7 8 9 10 11 12 APA2121 TO P View 24 23 22 21 20 19 18 17 16 15 14 13 G ND RLINEIN S HU TD O W N R OU T+ RHPIN VDD PVDD C LK R OU TSE/BTL PC-BEEP G ND Thermal Pad APA2120/1 Bottom View APA2120 APA2121 Multiple Input Selection PCBEEP Control Input SE/BTL PCBEN HP/LINE - Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 5 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Pin Function Description Pin Name GND PCBEN HP/LINE VOLUME LOUT+ LLINEIN LHPIN PVDD RBYPASS LOUTLBYPASS BYPASS PC_BEEP SE/BTL ROUTCLK VDD RHPIN ROUT+ SHUTDOWN RLINEIN No 1,12, 13,24 2 2 3 4 5 6 7,18 8 9 10 11 14 15 16 17 19 20 21 22 23 I/P O/P I/P I/P Config. Description Ground connection, Connected to thermal pad. I/P I/P O/P I/P O/P I/P O/P I/P I/P I/P O/P BEEP mode control input, active H, for APA2120 only Multi-input selection input, headphone mode when held high, line-in mode when held low for APA2121 only. Input signal for internal volume gain setting. Left channel positive output in BTL mode and SE mode. Left channel line input terminal, selected when HP/LINE is held low. Left channel headphone input terminal, selected when HP/LINE is held high. Supply voltage only for power amplifier. Right channel bypass voltage. Left channel negative output in BTL mode and high impedance in SE mode. Left channel bias voltage generator. Bias voltage generator PCBEP signal input Output mode control input, high for SE output mode and low for BTL mode. Right channel negative output in BTL mode and high impedance in SE mode. Clock signal generator Supply voltage for internal circuit excepting power amplifier. Right channel headphone input terminal, selected when HP/LINE is held high. Right channel positive output in BTL mode and SE mode. It will be into shutdown mode when pull low. Right channel line input terminal, selected when HP/LINE is held low. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 6 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Control Input Table For APA2120 SE/BTL X L H X SHUTDOWN L H H X PC-BEEP Disable Disable Disable Enable Operating mode Shutdown mode Line input, BTL out HP input, SE out PCBEEP input, BTL out For APA2121 SE/BTL X L L H H X HP/LINE X L H L H X SHUTDOWN L H H H H X PC-BEEP Disable Disable Disable Disable Disable Enable Operating mode Shutdown mode Line input, BTL out HP input, BTL out Line input, SE out HP input, BTL out PCBEEP input, BTL out Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 7 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Application Circuit APA2120 VDD 0 0.1F 100F PVDD VDD GND 1F L-LINE 1F LLINEIN LHPIN MUX LOUT+ 220F 1k L-HP 4 1F R-LINE 1F RLINEIN RHPIN VDD BYPASS MUX Volume Control LOUTLBYPASS 2.2F BYPASS ROUT+ 220F 1k SE/BTL Control Pin Ring R-HP Sleeve Tip Headphone Jack 50k VOLUME VDD 4 100k SE/BTL SE/BTL ROUTRBYPASS Shutdown Signal BEEP Signal PCBEN Signal SHUTDOWN 0.47F Shutdown ckt PCBEEP PCBEN PC-BEEP ckt Clock Gen CLK 47nF Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 8 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Application Circuit APA2121 VDD 0 0.1F VDD GND 100F PVDD 1F L-LINE 1F LLINEIN LHPIN MUX LOUT+ 220F 1k L-HP 4 1F R-LINE 1F RLINEIN RHPIN VDD BYPASS MUX Volume Control LOUTLBYPASS 2.2F BYPASS ROUT+ 220F SE/BTL Control Pin Ring R-HP Sleeve Tip Headphone Jack 50k VOLUME HP/LINE Signal 100k HP/LINE HP/LINE 1k VDD 4 SE/BTL SE/BTL ROUTRBYPASS Shutdown Signal BEEP Signal SHUTDOWN Shutdown ckt PCBEEP 0.47F PC-BEEP ckt CLK Clock Gen 47nF Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 9 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Volume Control Table_BTL Mode Supply Voltage Vdd=5V Gain(dB) 20 18 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -80 High(V) 0.12 0.23 0.34 0.46 0.57 0.69 0.80 0.91 1.03 1.14 1.25 1.37 1.48 1.59 1.71 1.82 1.93 2.05 2.16 2.28 2.39 2.50 2.62 2.73 2.84 2.96 3.07 3.18 3.30 3.41 3.52 5.00 Low(V) 0.00 0.17 0.28 0.39 0.51 0.62 0.73 0.84 0.96 1.07 1.18 1.29 1.41 1.52 1.63 1.74 1.85 1.97 2.08 2.19 2.30 2.42 2.53 2.64 2.75 2.87 2.98 3.09 3.20 3.32 3.43 3.54 Hysteresis(mV) 52 51 50 49 47 46 45 44 43 41 40 39 38 37 35 34 33 32 30 29 28 27 26 24 23 22 21 20 18 17 16 Recommended Voltage(V) 0 0.20 0.31 0.43 0.54 0.65 0.77 0.88 0.99 1.10 1.22 1.33 1.44 1.56 1.67 1.78 1.89 2.01 2.12 2.23 2.35 2.46 2.57 2.69 2.80 2.91 3.02 3.14 3.25 3.36 3.48 5 Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 10 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Characteristics THD+N vs. Frequency 10 10 THD+N vs. Output Power VDD=5V RL=3 AV=2 BTL VDD=5V RL=3 Po=1.75W BTL THD+N (%) 0.1 AV=10 AV=2 THD+N (%) 1 1 f=20kHz 0.1 f=1kHz AV=5 f=20Hz 0.01 20 0.01 10m 100m 1 23 100 1k 20k Frequency (Hz) Output Power (W) THD+N vs. Frequency 10 10 THD+N vs. Output Power VDD=5V RL=4 AV=2 BTL VDD=5V RL=4 Po=1.5W BTL THD+N (%) THD+N (%) 1 1 f=20kHz 0.1 AV=2 AV=5 AV=10 0.1 f=1kHz f=20Hz 0.01 20 50 100 200 500 1k 2k 5k 20k 0.01 100m 200m 500m 800m 2 3 Frequency (W) Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 11 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Characteristics (Cont.) THD+N vs. Frequency 10 10 THD+N vs. Output Power VDD=5V RL=8 AV=2 BTL VDD=5V RL=8 Po=1.0W BTL THD+N (%) 1 THD+N (%) 1 f=20kHz 0.1 AV=2 AV=5 AV=10 0.1 f=1kHz f=20Hz 0.01 10m 0.01 20 10 0 1k 20 k 100m 1 2 Frequency (Hz) Output Power (W) THD+N vs. Frequency 10 THD+N vs. Output Power 10 VDD=5V RL=8 Po=250mW SE VDD=5V RL=8 AV=2 BTL THD+N (%) THD+N (%) 1 1 f=20kHz 0 .1 0.1 AV=1 AV=5 f=20Hz AV=2.5 f=1kHz 0 .01 10m 0.01 20 100 1k 20k 1 0 0m 5 0 0m Frequency (Hz) Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 12 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Characteristics (Cont.) THD+N vs. Frequency 10 THD+N vs. Output Power 10 VDD=5V RL=16 Po=100mW SE VDD=5V RL=16 AV=1 BTL THD+N (%) THD+N (%) 1 1 f=20Hz 0.1 f=20kHz 0.1 AV=2 AV=1 AV=2.5 0.01 20 f=1kHz 50 100 200 500 1k 2k 5k 20k 0.01 10m 100m 300m Frequency (Hz) Output Power (W) THD+N vs. Frequency 10 THD+N vs. Output Power 10 5 VDD=5V RL=32 Po=75mW SE VDD=5V RL=32 AV=1 BTL f=20kHz THD+N (%) 0.1 AV=2.5 AV=1 THD+N (%) 1 1 0.1 f=20Hz f=1kHz AV=5 0.01 20 100 1k 20k 0.01 10 m 50 m 10 0m 20 0m Frequency (Hz) Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 13 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Characteristics (Cont.) THD+N vs. Frequency 10 THD+N vs. Output Swing 10 VDD=5V RL=10 Vo=1VRMS SE VDD=5V RL=10 AV=1 SE THD+N (%) 0.1 AV=2.5 AV=1 THD+N (%) 1 1 0.1 f=20kHz f=1kHz f=20Hz AV=5 0.01 20 10 0 1k 20 k 0.01 100m 500m 1 2 3 Frequency (Hz) Output Swing (VRMS) Crosstalk vs. Frequency +0 Crosstalk vs. Frequency VDD=5V RL=32 -2 0 Po=75mW AV=1 SE +0 VDD=5V RL=8 -20 Po=1.0W AV=2 BTL Crosstalk (dB) -40 Crosstalk (dB) -4 0 -60 -6 0 -80 R-ch to L-ch L-ch to R-ch -8 0 R-ch to L-ch L-ch to R-ch -1 00 -10 0 -12 0 20 1 00 1k 2 0k -1 20 20 100 1k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 14 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Characteristics (Cont.) Noise Floor vs. Frequency 100u 50u 10 0u Noise Floor vs. Frequency VDD=5V RL=32 50 u AV=1 SE Noise Floor (VRMS) Noise Floor (VRMS) No Filter 20u 20 u A-Weight 10u 5u No Filter 10 u 5u A-Weight 2u VDD=5V RL=8 AV=2 BTL 100 1k 20k 2u 1u 20 1u 20 10 0 1k 20 k Frequency (Hz) Frequency (Hz) Noise Floor vs. Frequency 1 0 0u Power Dissipation vs. Output Power 0 .2 0 .1 8 Power Dissipation (W) Noise Floor (VRMS) VDD=5V RL=10K 5 0 u AV=1 SE 20u 10u 0 .1 6 0 .1 4 0 .1 2 0 .1 0 .0 8 0 .0 6 0 .0 4 0 .0 2 No Filter RL=8 A-Weight 5u RL=16 RL=32 VDD=5V AV=1 SE 0 0 .0 5 0 .1 0 .1 5 0 .2 0 .2 5 0 .3 0 .3 5 0 .4 2u 1u 20 0 100 1k 20k Frequency (Hz) Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 15 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Characteristics (Cont.) Power Dissipation vs. Output Power 1 .8 1 .6 20 1 7 .5 Supply Current vs. Supply Voltage Power Dissipation (W) Suuply Current (mA) 1 .4 1 .2 1 0 .8 0 .6 RL=3 15 1 2 .5 10 7 .5 5 2 .5 BTL RL=4 SE RL=8 0 .4 0 .2 0 0 0 .5 1 1 .5 2 2 .5 VDD=5V AV=2 BTL No Load 1 1 .5 2 2 .5 3 3 .5 4 4 .5 5 5 .5 Output Power (W) Supply Voltage (V) Output Power vs. Supply Voltage 2 .0 1 .8 1 .6 160 Output Power vs. Supply Voltage RL=32 AV=1 SE RL=8 AV=2 BTL 140 Output Power (mW) Output Power (W) 120 100 80 60 40 20 0 1 .4 1 .2 1 .0 0 .8 0 .6 0 .4 0 .2 0 2 .5 3 3 .5 4 4 .5 5 5 .5 THD+N=10% THD+N=10% THD+N=1% THD+N=1% 2.5 3 3.5 4 4.5 5 5.5 Supply Voltage (V) Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 16 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Characteristics (Cont.) Output Power vs. Load Resistance 3 2.5 VDD=5V AV=2 BTL Output Power vs. Load Resistance 0.7 0.6 VDD=5V AV=1 SE Output Power (W) Output Power (W) 2 1.5 1 THD+N=10% 0.5 0.4 0.3 0.2 0.1 0 THD+N=1% THD+N=10% 0.5 0 THD+N=1% 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 4 8 12 16 20 24 28 32 36 40 44 48 52 56 6064 Load Resistance () Load Resistance () Close Loop Response +12 Close Loop Response +6 +4 VDD=5V RL=8 +10 AV=2 BTL CO=330F VDD=5V RL=32 AV=1 SE CO=330F Loop Gain (dB) +8 Loop Gain (dB) +2 +6 +0 +4 AV=2 AV=5 AV=10 -2 AV=1 AV=2.5 AV=5 +2 -4 -0 20 100 1k 20k -6 20 100 1k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 17 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Typical Characteristics (Cont.) PSRR vs. Frequency +0 Ripple Rejection Ratio (dB) -2 0 VDD=5V Vin=100mVRMS RL=8 Cbypass=2.2F BTL 66 -4 0 -6 0 SE -8 0 20 100 1k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 18 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Application Descriptions BTL Operation The APA2120/1 output stage (power amplifier) has two pairs of operational amplifiers internally, allowed for different amplifier configurations. OUT+ BTL Operation (Cont.) Four times the output power same conditions. A BTL configuration, such as the one used in APA2120/1, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, no Volume Control am plifier output signal OP1 need DC voltage exists across the load. This elimiRL OUTOP2 nates the need for an output coupling capacitor which is required in a single supply, SE configuration. Single-Ended Operation Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33F to 1000F) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described still hold with the addition of the following relationship: 1 1 << 1 Cbypass x 125k RiCi RLCC Output SE/BTL Operation The ability of the APA2120/1 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. (1) Vbias Circuit Figure 1: APA2120/1 internal configuration (each channel) The power amplifier's OP1 gain is setting by internal unity-gain and input audio signal is come from internal volume control amplifier, while the second amplifier OP2 is internally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the input to OP2, which results in the output signals of with both amplifiers with identical in magnitude, but out of phase 180. Consequently, the differential gain for each channel is 2 x (Gain of SE mode). By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 19 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Application Descriptions (Cont.) Output SE/BTL Operation (Cont.) Internal to the APA2120/1, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input controls the operation of the follower amplifier that drives LOUT- and ROUT-. * When SE/BTL is held low, the OP2 is turn on and the APA2120/1 is in the BTL mode. *When SE/BTL is held high, the OP2 is in a high output impedance state, which configures the APA2120/1 as SE driver from OUT+. IDD is reduced by approximately one-half in SE mode. Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application Circuit. 1k VDD 100k SE/BTL Sleeve Control Pin Ring Output SE/BTL Operation (Cont.) Resistor 1k then pulls low the SE/BTL pin, enabling the BTL function. Volume Control Function APA2120/1 has an internal stereo volume control whose setting is a function of the DC voltage applied to the VOLUME input pin. The APA2120/1 volume control consists of 32 steps that are individually selected by a variable DC voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from 20dB to -80dB. Each gain step corresponds to a specific input voltage range, as shown in table. To minimize the effect of noise on the volume control pin, which can affect the selected gain level, hysteresis and clock delay are implemented. The amount of hysteresis corresponds to half of the step width, as shown in volume control graph. Gain_BT L m ode 20 16 12 8 4 APA2021 volum e control curve Forward Backward Tip Headphone Jack Figure 2: SE/BTL input selection by phonejack plug In Figure 2, input SE/BTL operates as follows : When the phonejack plug is inserted, the 1k resistor is disconnected and the SE/BTL input is pulled high and enables the SE mode. When the input goes high, the OUT- amplifier is shutdown causing the speaker to mute. The OUT+ amplifier then drives through the output capacitor (CC) into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100k and 1k. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 20 0 -4 -8 -12 -16 -20 -24 -28 -32 -36 -40 -44 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 (V) Figure 3: Gain setting vs VOLUME pin voltage www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Application Descriptions (Cont.) Volume Control Function (Cont.) For highest accuracy, the voltage shown in the `recommended voltage' column of the table is used to 80 Ri(k) 120 100 Ri vs Gain(BTL) select a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. The gain levels are 2dB/step from 20dB to -40dB in BTL mode, and the last step at -80dB as mute mode. Input Resistance, Ri The gain for each audio input of the APA2120/1 is set by the internal resistors (Ri and Rf) of volume control amplifier in inverting configuration. RF (2) Ri RF (3) BTL Gain = -2 x Ri BTL mode operation brings the factor of 2 in the gain SE Gain = AV = equation due to the inverting amplifier mirroring the voltage swing across the load. For the varying gain setting, APA2120/1 generates each input resistance on figure 4. The input resistance will affect the low frequency performance of audio signal. The minmum input resistance is 10k when gain setting is 20dB and the resistance will ramp up when close loop gain below 20dB. The input resistance has wide variation (+/-10%) caused by process variation. The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 10k and the specification calls for a flat bass response down to 100Hz. Equation is reconfigured as follow : Ci= 1 2x10kxfC (5) FC(highpass)= 60 40 20 0 -40 -30 -20 -10 0 10 20 Gain(dB) Figure 4: Input resistance vs Gain setting Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri (10k) form a high-pass filter with the corner frequency determined in the follow equation : 1 2x10kxCi (4) Consider to input resistance variation, the Ci is 0.16F so one would likely choose a value in the range of 0.22F to 1.0F. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 21 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Application Descriptions (Cont.) Input Capacitor, Ci (Cont.) A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. sPlease note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor, Cbypass As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitors located on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger bypass capacitor will improve PSRR due to increased supply stability. Typical applications employ a 5V regulator with 1.0F and a 0.1F bypass capacitor as supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2120/1. The selection of bypass capacitors, especially Cbypass, is thus dependent upon desired PSRR requirements, click and pop performance. On the chip, there are three bypass pins for used, and they are tied together in the internal circuit. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 22 www.anpec.com.tw Effective Bypass Capacitor, Cbypass (Cont.) The effective capacitance is the Cbypass=(Cb// CLbyasss//CRbypass). When absolute minimum cost and/or component space is required, one bypass capacitor can be used. To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the relationship shown in equation (6) should be maintained. 1 1 << Cbypass x 125k 100k x Ci (6) The bypass capacitor is fed thru from a 125k resistor inside the amplifier and the 100k is maximum input resistance of (Ri+ Rf). Bypass capacitor, Cb, values of 3.3F to 10F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. The bypass capacitance also effects to the start up time. It is determined in the following equation : Tstart up = 5 x (Cbypass x 125K) Output Coupling Capacitor, Cc In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation. FC(highpass)= 1 2RLCC (8) (7) DataSheet 4 U .com www..com APA2120/2121 Application Descriptions (Cont.) Output Coupling Capacitor, Cc (Cont.) For example, a 330F capacitor with an 8 speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load. Power Supply Decoupling, Cs The APA2120/1 provides PVDD and VDD two independent power inputs for used. PVDD is used for power amplifier only and VDD is used for volume control amplifier and internal circuit excepting power amplifier. The APA2120/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1F placed as close as possible to the device VDD and PVDD lead works best. For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended. Optimizing Depop Circuitry Circuitry has been included in the APA2120/1 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage ramp up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cbypass can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of Cbypass, turnon pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turnon time for this device. There is a linear relationship between the size of Cbypass and the turn-on time. In a SE configuration, the output coupling capacitor, CC, is of particular concern. This capacitor discharges through the internal 10k resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1k resistor can be placed in parallel with the internal 10k resistor. The tradeoff for using this resistor is an increase in quiescent current. In the most cases, choosing a small value of Ci in the range of 0.33F to 1F, Cb being equal to 4.7F and an external 1k resistor should be placed in parallel with the internal 10k resistor should produce a virtually clickless and popless turn-on. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 23 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Application Descriptions (Cont.) Optimizing Depop Circuitry (Cont.) A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. Shutdown Function In order to reduce power consumption while not in use, the APA2120/1 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch between ground and the supply VDD to provide maximum device performance. By switching the SHUTDOWN pin to low, the amplifier enters a low-current state, IDD<50A. APA2120/1 is in shutdown mode, except PC-BEEP detect circuit. On normal operating, SHUTDOWN pin pull to high level to keeping the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changes. Input HP/LINE Operation APA2120/1 amplifier has two separate inputs for each of the left and right stereo channels. The APA2120 and APA2121 have different control input by SE/BTL and HP/LINE, respectively. APA2120 internal multiplexor is selected by SE/BTL control input. Refer to the `Output SE/BTL Operation', the voltage divider of 100k and 1k sets the voltage at the SE/BTL pin to be approximately 50mV when no phonejack plugged into the system. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 24 Input HP/LINE Operation (Cont.) This logic-low voltage at the SE/BTL pin makes APA2120 into LINE input mode operation. It becomes HP input mode when phonejack plugged. An internal multiplexor selects the input to connect to the amplifier based on the state of the HP/LINE pin of the APA2121. * To select the LINE inputs, set HP/LINE pin to low level. * To enable the HP(headphone) inputs, set HP/LINE pin to high level. As APA2121, HP/LINE input multiplexor, and SE/BTL output operating mode have independent control paths, which can be used for multiple audio input system. This function will be the same as APA2120 when HP/LINE and SE/BTL are tied together. PC-BEEP Detection APA2120/1 integrates a BEEP detect circuit for NOTEBOOK PC. When BEEP signal is provided on PCBEEP input pin, the BEEP mode is active. APA2120/1 will force to BTL mode and the internal gain is fixed at -10dB. The PCBEEP signal becomes the amplifier input signal and plays on the speaker without coupling capacitor. It will be out of shutdown mode whenever BEEP mode is enabled. APA2120/ 1 will return to previous setting when it is out of BEEP mode. The input impedance is 100k on PCBEEP input pin. APA2120 provides extra PCBEN control input signal to force IC into BEEP mode. The BEEP mode will be enabled when PCBEN goes to high level. When BEEP mode is overridden, the signal from PCBEEP will pass to speaker directly. www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Application Descriptions (Cont.) Clock Generator APA2120/1 integrates a clock block to avoid volume control function abnormal when VOLUME control signal with spike or noise. APA2120/1 changes each step of volume gain after four clock cycles to make sure control signal ready. It provides 130kHz frequency if no capacitor place on CLK pin to ground. The larger capacitance will slow down the and clock frequency. A capacitor 33nF between CLK to ground and will generates 147Hz frequency on CLK pin. BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. Efficiency = Where : PO = VORMS x VORMS = VPxVP 2RL RL VORMS = VP 2 (10) (11) 1.00 1.25 66.67 78.13 0.30 0.32 4.00 4.47 0.5 0.35 BTL Amplifier Efficiency (Cont.) Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8 loads and a 5V supply, the maximum draw on the power supply is almost 3W. A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation, V DD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency (9) analysis to choose the correct supply voltage and speaker impedance for the application. Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) 0.25 0.50 31.25 47.62 0.16 0.21 2.00 2.83 0.55 0.55 PO PSUP PSUP = VDD x IDDRMS = VDD x 2VP RL Efficiency of a BTL configuration : PO VPxVP ) / (VDD x 2VP ) = VP =( 2VDD PSUP 2RL RL (12) **High peak voltages cause the THD to increase. Table 1. Efficiency Vs Output Power in 5-V/8 BTL Systems Table 1 calculates efficiencies for four different output power levels. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 25 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Application Descriptions (Cont.) Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation13 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. SE mode : PD,MAX= VDD2 22RL (13) Power Dissipation (Cont.) Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Pad Considerations The thermal pad must be connected to ground. The package with thermal pad of the APA2120/1 requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA2120/1 4 will go into thermal shutdown when driving a 4 load. The thermal pad on the bottom of the APA2120/1 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to (15) conduct heat away from the thermal pad should be as large as practical. For TSSOP-24 package with thermal pad, the thermal resistance (JA) is equal to 45 C/W. Since the maximum junction temperature (TJ,MAX) of APA2120/1 is 150C and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation16. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 26 In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. BTL mode : PD,MAX= 4VDD2 22RL (14) Since the APA2120/1 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2120/1 does not require extra heatsink. The power dissipation from equation14, assuming a 5V-power supply and an 8 load, must not be greater than the power dissipation that results from the equation15 : TJ,MAX - TA PD,MAX= JA If the ambient temperature is higher than 25C, a larger copper plane or forced-air cooling will be required to keep the APA2120/1 junction temperature below the thermal shutdown temperature (150C). In higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the IC out of thermal shutdown. www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Packaging Information T S S O P / T S S O P -P ( R eference JE D E C R egistration M O -153) e N 2x E/2 E1 E 1 2 3 e/2 D A2 A ( 2) GAUGE PLANE S b D1 A1 EXPOSED THERMAL PAD ZONE E2 0.25 L (L1) ( 3) 1 BOTTOM VIEW (THERMALLY ENHANCED VARIATIONDS ONLY) D im A A1 A2 D M illim eters Inches D1 e E E1 E2 L L1 R R1 S 1 2 3 M ax. 1.2 0.00 0.15 0.80 1.05 6.4 (N =20P IN ) 6.6 (N =20P IN ) 7.7 (N =24P IN ) 7.9 (N =24P IN ) 9.6 (N =28P IN ) 9.8 (N =28P IN ) 4.2 B S C (N =20P IN ) 4.7 B S C (N =24P IN ) 3.8 B S C (N =28P IN ) 0.65 B S C 6.40 B S C 4.30 4.50 3.0 B S C (N =20P IN ) 3.2 B S C (N =24P IN ) 2.8 B S C (N =28P IN ) 0.45 0.75 1.0 R E F 0.09 0.09 0.2 0 8 12 R E F 12 R E F 27 M in. M ax. 0.047 0.000 0.006 0.031 0.041 0.252 (N =20P IN ) 0.260 (N =20P IN ) 0.303 (N =24P IN ) 0.311 (N =24P IN ) 0.378 (N =28P IN ) 0.386 (N =28P IN ) 0.165 B S C (N =20P IN ) 0.188 B S C (N =24P IN ) 0.150 B S C (N =28P IN ) 0.026 B S C 0.252 B S C 0.169 0.177 0.118 B S C (N =20P IN ) 0.127 B S C (N =24P IN ) 0.110 B S C (N =28P IN ) 0.018 0.030 0.039R E F 0.004 0.00 4 0.008 0 8 12 R E F 12 R E F www.anpec.com.tw M in. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 DataSheet 4 U .com www..com APA2120/2121 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) Reference JEDEC Standard J-STD-020A APRIL 1999 temperature Peak temperature 183C Pre-heat temperature Time Classification Reflow Profiles Convection or IR/ Convection Average ramp-up rate(183C to Peak) 3C/second max. 120 seconds max Preheat temperature 125 25C) 60 - 150 seconds Temperature maintained above 183C Time within 5C of actual peak temperature 10 -20 seconds Peak temperature range 220 +5/-0C or 235 +5/-0C Ramp-down rate 6 C /second max. 6 minutes max. Time 25C to peak temperature VPR 10 C /second max. 60 seconds 215-219C or 235 +5/-0C 10 C /second max. Package Reflow Conditions pkg. thickness 2.5mm and all bgas Convection 220 +5/-0 C VPR 215-219 C IR/Convection 220 +5/-0 C pkg. thickness < 2.5mm and pkg. volume 350 mm pkg. thickness < 2.5mm and pkg. volume < 350mm Convection 235 +5/-0 C VPR 235 +5/-0 C IR/Convection 235 +5/-0 C www.anpec.com.tw Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 28 DataSheet 4 U .com www..com APA2120/2121 Reliability test program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C , 5 SEC 1000 Hrs Bias @ 125 C 168 Hrs, 100 % RH , 121C -65C ~ 150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 100mA Carrier Tape & Reel Dimensions Po E P1 P D t F W Bo Ao Ko D1 T2 J C A B T1 Application A 330 1 B 100 ref D 1.5 +0.1 C 13 0.5 D1 1.5 min J 2 0.5 Po 4.0 0.1 T1 16.4 0.2 P1 2.0 0.1 T2 2 0.2 Ao 6.9 0.1 W 16 0.3 Bo 8.3 0.1 P 12 0.1 Ko 1.5 0.1 E 1.750.1 t 0.30.05 TSSOP- 24 F 7.5 0.1 Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 29 www.anpec.com.tw DataSheet 4 U .com www..com APA2120/2121 Cover Tape Dimensions Application TSSOP- 24 Carrier Width 16 Cover Tape Width 21.3 Devices Per Reel 2000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 30 www.anpec.com.tw DataSheet 4 U .com |
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